ADZS-21364-EZLITE【PDF 29/60 页】KIT EVAL EZ LITE ADDS-21364

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync (FS) delay and frame sync setup and

hold, 2) data delay and data setup and hold, and 3) serial clock

(SCLK) width.

Table 24. Serial Ports—External Clock

Serial port signals are routed to the DAI_P20–1 pins using the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

K and B Grade

Y Grade

Parameter

Min

Max

Max

Unit

Timing Requirements

t SFSE 1

Frame Sync Setup Before SCLK

t HFSE

1

(Externally Generated Frame Sync in Either Transmit or Receive Mode)

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode)

2.5

2.5

ns

ns

t SDRE

1

t HDRE 1

t SCLKW

t SCLK

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

SCLK Width

SCLK Period

2.5

2.5

(t PCLK × 4) ÷ 2 – 2

t PCLK × 4

ns

ns

ns

ns

Switching Characteristics

t DFSE 2

Frame Sync Delay After SCLK

t HOFSE 2

(Internally Generated Frame Sync in Either Transmit or Receive Mode)

Frame Sync Hold After SCLK

(Internally Generated Frame Sync in Either Transmit or Receive Mode)

2

9.5

11

ns

ns

t DDTE 2

Transmit Data Delay After Transmit SCLK

9.5

11

ns

t HDTE

2

Transmit Data Hold After Transmit SCLK

2

ns

1

2

Referenced to sample edge.

Referenced to drive edge.

Table 25. Serial Ports—Internal Clock

K and B Grade

Y Grade

Parameter

Min

Max

Max

Unit

Timing Requirements

t SFSI 1

Frame Sync Setup Before SCLK

t HFSI 1

(Externally Generated Frame Sync in Either Transmit or Receive Mode)

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode)

7

2.5

ns

ns

t SDRI 1

t HDRI 1

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

7

2.5

ns

ns

Switching Characteristics

t DFSI 2

t HOFSI 2

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode)

–1.0

3

3.5

ns

ns

t DFSIR

2

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)

8 9.5 ns

t HOFSIR 2

t DDTI 2

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)

Transmit Data Delay After SCLK

–1.0 ns

3 4.0 ns

t HDTI

2

Transmit Data Hold After SCLK

–1.0 ns

t SCLKIW

Transmit or Receive SCLK Width

2 × t PCLK – 2 2 × t PCLK + 2 2 × t PCLK + 2 ns

1

2

Referenced to the sample edge.

Referenced to drive edge.

Rev. J |

Page 29 of 60 |

July 2013

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